Abstract
A memory and compiler co-optimization aimed at reducing low-level memory accesses using software and hardware locality optimizations is discussed. The analysis of conflict-free access to parallel memories and alignment networks using algebra of non-singular Boolean matrices is also discussed. An effective compiler heuristic is proposed for finding a storage matrix that minimizes overall memory access time. The results show that a memory utilization above 83% is achievable by the storage scheme for 64 memories.
| Original language | English |
|---|---|
| Pages (from-to) | 123-163 |
| Number of pages | 41 |
| Journal | International Journal of Parallel Programming |
| Volume | 32 |
| Issue number | 2 |
| DOIs | |
| State | Published - Apr 2004 |
Keywords
- Access patterns
- Compiler optimization
- Embedded systems
- Parallel memory
- Streamed computations
ASJC Scopus subject areas
- Software
- Theoretical Computer Science
- Information Systems