TY - GEN
T1 - Area-time optimal adder with relative placement generator
AU - Farooqui, Aamir A.
AU - Oklobdzija, Vojin G.
AU - Sait, Sadiq M.
PY - 2003
Y1 - 2003
N2 - This paper presents design of an adder generator, for the production of area-time-optimal adders. A unique feature of the proposed generator is its integrated synthesis and layout environment achieved by providing relative placement information to the synthesis tool. Adders produced by this generator are dynamically configured for a given technology library, wire-load model, delay, and area goal. The adder architecture used in this generator is a hybrid of Brent & Kung, carry select, and ripple carry adders. When compared with standard cell fast adders, a 20%-50% reduction in area with comparable delays is achieved. The reduction comes from a judicious selection of ripple carry or carry select adders based on computation of delays. When performance is being met, the carry select adders are replaced with ripple carry adders. The proposed generator has been integrated into a commercially available high-performance datapath design tool.
AB - This paper presents design of an adder generator, for the production of area-time-optimal adders. A unique feature of the proposed generator is its integrated synthesis and layout environment achieved by providing relative placement information to the synthesis tool. Adders produced by this generator are dynamically configured for a given technology library, wire-load model, delay, and area goal. The adder architecture used in this generator is a hybrid of Brent & Kung, carry select, and ripple carry adders. When compared with standard cell fast adders, a 20%-50% reduction in area with comparable delays is achieved. The reduction comes from a judicious selection of ripple carry or carry select adders based on computation of delays. When performance is being met, the carry select adders are replaced with ripple carry adders. The proposed generator has been integrated into a commercially available high-performance datapath design tool.
UR - https://www.scopus.com/pages/publications/0038082078
M3 - Conference contribution
AN - SCOPUS:0038082078
SN - 0780377613
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - V141-V144
BT - Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003
Y2 - 25 May 2003 through 28 May 2003
ER -