Analysis of harmonic reduction for synchronized phase-shifted parallel PWM inverters with current sharing reactors

Renewable energy sources are quickly becoming incorporated into increasingly distributed electrical utility grids. An ever present issue when interfacing these sources is that of harmonic distortion reduction at the inter-tie point. One very interesting approach to reduce harmonic distortion is to synchronize power transistor operation for inverters operating in parallel. In this paper, a rarely employed technique for harmonic reduction using synchronized phase shifted parallel PWM inverters with current-sharing reactors is presented and analyzed. Using the technique presented inverter output distortion can be reduced significantly, for example total harmonic reduction can be reduced typically in half using just two synchronized phase-shifted parallel inverters (our simulation and experimental studies indicate that even smaller distortion reduction factors can be achieved). We present analyses for two and three phase-shifted inverters operated in parallel employing current sharing reactors. Our analyses consider the impact of a wide range of phase-shift delays on net output total harmonic distortion, with the phase-shift delay from zero to one entire cycle of the fundamental component. Some results are expected, such as a dramatic increase in distortion when the fundamental components between multiple inverters tend to cancel out, on the other hand it is interesting to observe a leveling-off, and gradual, smooth increase in the distortion reduction factor over a significant portion of the phase-shift delay variable.