An improved asymmetrical multi-level inverter topology with boosted output voltage and reduced components count

  • M. Saad Bin Arif
  • , Uvais Mustafa
  • , Marif Daula Siddique
  • , Shahbaz Ahmad
  • , Atif Iqbal*
  • , Ratil Hasnat Ashique
  • , Shahrin bin Ayob
  • *Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

40 Scopus citations

Abstract

This paper presents an improved Multi-level Inverter topology utilizing the concept of boosting-capacitor and two DC sources with reduced switches count for generating 17-level output. The topology employs 10 unidirectional switches including one bidirectional switch. Comparison with other recent topologies shows that the proposed topology employs a reduced number of devices and better performance. The topology combines the modularity of H-Bridge with the boosting capacity of the switched capacitor topology. Special care is taken while designing the switching strategy for voltage balancing of the capacitors. The authors also have generalized the topology to produce ‘n’ level output. Relevant expressions are also formed and reported. Experimental validation, as well as simulation, is performed, and results are verified. Nearest level control is used as the modulation technique.

Original languageEnglish
Pages (from-to)2052-2066
Number of pages15
JournalIET Power Electronics
Volume14
Issue number12
DOIs
StatePublished - 16 Sep 2021
Externally publishedYes

Bibliographical note

Publisher Copyright:
© 2021 The Authors. IET Power Electronics published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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