An efficient test vector compression technique based on geometric shapes

  • Saif Al Zahir*
  • , Aiman El-Maleh
  • , Esam Khan
  • *Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

One of the prime challenges of testing a system-on-achip (SOC) is to reduce the required test data size. In this paper, we introduce a novel geometric shapes based compression / decompression scheme that substantially reduces the amount of test data and hence reduces test time. The proposed scheme is based on reordering the test vectors in such a way that enables the generation of geometric shapes that can be highly compressed via perfect lossless compression. Experimental results on ISCAS benchmark circuits demonstrate the effectiveness of the proposed technique in achieving very high compression ratio. Compared to published results, our technique achieves signijkantly higher compression ratio.

Original languageEnglish
Title of host publicationICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1561-1564
Number of pages4
ISBN (Print)0780370570, 9780780370579
StatePublished - 2001

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume3

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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