An efficient test relaxation technique for combinational & full-scan sequential circuits

A. El-Maleh; A. Al-Suwaiyan

doi:10.1109/VTS.2002.1011111

An efficient test relaxation technique for combinational & full-scan sequential circuits

A. El-Maleh, A. Al-Suwaiyan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper we propose a novel and efficient test relaxation technique for combinational and full-scan sequential circuits. The proposed technique is faster than the brute-force test relaxation method by several orders of magnitude. The application of the technique in improving the effectiveness of test compaction and compression is illustrated.

Original language	English
Title of host publication	Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002
Publisher	IEEE Computer Society
Pages	53-59
Number of pages	7
ISBN (Electronic)	0769515703
DOIs	https://doi.org/10.1109/VTS.2002.1011111
State	Published - 2002

Publication series

Name	Proceedings of the IEEE VLSI Test Symposium
Volume	2002-January

Bibliographical note

Publisher Copyright:
© 2002 IEEE.

Keywords

Automatic test pattern generation
Automatic testing
Circuit faults
Circuit testing
Compaction
Sequential analysis
Sequential circuits
System testing
Test pattern generators
Very large scale integration

ASJC Scopus subject areas

Computer Science Applications
Electrical and Electronic Engineering

Access to Document

10.1109/VTS.2002.1011111

Cite this

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title = "An efficient test relaxation technique for combinational & full-scan sequential circuits",

abstract = "Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper we propose a novel and efficient test relaxation technique for combinational and full-scan sequential circuits. The proposed technique is faster than the brute-force test relaxation method by several orders of magnitude. The application of the technique in improving the effectiveness of test compaction and compression is illustrated.",

keywords = "Automatic test pattern generation, Automatic testing, Circuit faults, Circuit testing, Compaction, Sequential analysis, Sequential circuits, System testing, Test pattern generators, Very large scale integration",

author = "A. El-Maleh and A. Al-Suwaiyan",

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year = "2002",

doi = "10.1109/VTS.2002.1011111",

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An efficient test relaxation technique for combinational & full-scan sequential circuits. / El-Maleh, A.; Al-Suwaiyan, A.
Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002. IEEE Computer Society, 2002. p. 53-59 1011111 (Proceedings of the IEEE VLSI Test Symposium; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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KW - Automatic test pattern generation

KW - Automatic testing

KW - Circuit faults

KW - Circuit testing

KW - Compaction

KW - Sequential analysis

KW - Sequential circuits

KW - System testing

KW - Test pattern generators

KW - Very large scale integration

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M3 - Conference contribution

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BT - Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002

PB - IEEE Computer Society

ER -

An efficient test relaxation technique for combinational & full-scan sequential circuits

Abstract

Publication series

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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Cite this