An efficient network-on-chip architecture based on the Fat-Tree (FT) topology

A. Bouhraoua; M. E. Elrabaa

doi:10.1109/ICM.2006.373259

An efficient network-on-chip architecture based on the Fat-Tree (FT) topology

A. Bouhraoua^*
, M. E. Elrabaa

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Scopus citations

Abstract

A novel approach for an efficient network-on-chip using a modified Fat Tree is presented. Contention is eliminated and latency is reduced through an improved topology and router architecture. The adopted topology increases performance without a substantial increase in the routing cost. This is achieved by using an improved buffer-less, paremeterizable router architecture. The proposed router architecture is simple to implement yet can achieve the required packet collision avoidance. Simulation results that show the level of performance achieved by both the topology and the router architecture are presented. A throughput of more than 90% is achieved way above the 40-50% usually seen in other networks on chips.

Original language	English
Title of host publication	Proceedings of the International Conference on Microelectronics, ICM
Pages	28-31
Number of pages	4
DOIs	https://doi.org/10.1109/ICM.2006.373259
State	Published - 2006

Publication series

Name	Proceedings of the International Conference on Microelectronics, ICM

Keywords

ASICs
Interconnection networks
Networks-on-chip
Systems-on-chip

ASJC Scopus subject areas

Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ICM.2006.373259

Cite this

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title = "An efficient network-on-chip architecture based on the Fat-Tree (FT) topology",

abstract = "A novel approach for an efficient network-on-chip using a modified Fat Tree is presented. Contention is eliminated and latency is reduced through an improved topology and router architecture. The adopted topology increases performance without a substantial increase in the routing cost. This is achieved by using an improved buffer-less, paremeterizable router architecture. The proposed router architecture is simple to implement yet can achieve the required packet collision avoidance. Simulation results that show the level of performance achieved by both the topology and the router architecture are presented. A throughput of more than 90\% is achieved way above the 40-50\% usually seen in other networks on chips.",

keywords = "ASICs, Interconnection networks, Networks-on-chip, Systems-on-chip",

author = "A. Bouhraoua and Elrabaa, \{M. E.\}",

year = "2006",

doi = "10.1109/ICM.2006.373259",

language = "English",

isbn = "1424407656",

series = "Proceedings of the International Conference on Microelectronics, ICM",

pages = "28--31",

booktitle = "Proceedings of the International Conference on Microelectronics, ICM",

}

An efficient network-on-chip architecture based on the Fat-Tree (FT) topology. / Bouhraoua, A.; Elrabaa, M. E.
Proceedings of the International Conference on Microelectronics, ICM. 2006. p. 28-31 4243640 (Proceedings of the International Conference on Microelectronics, ICM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Bouhraoua, A.

AU - Elrabaa, M. E.

PY - 2006

Y1 - 2006

N2 - A novel approach for an efficient network-on-chip using a modified Fat Tree is presented. Contention is eliminated and latency is reduced through an improved topology and router architecture. The adopted topology increases performance without a substantial increase in the routing cost. This is achieved by using an improved buffer-less, paremeterizable router architecture. The proposed router architecture is simple to implement yet can achieve the required packet collision avoidance. Simulation results that show the level of performance achieved by both the topology and the router architecture are presented. A throughput of more than 90% is achieved way above the 40-50% usually seen in other networks on chips.

AB - A novel approach for an efficient network-on-chip using a modified Fat Tree is presented. Contention is eliminated and latency is reduced through an improved topology and router architecture. The adopted topology increases performance without a substantial increase in the routing cost. This is achieved by using an improved buffer-less, paremeterizable router architecture. The proposed router architecture is simple to implement yet can achieve the required packet collision avoidance. Simulation results that show the level of performance achieved by both the topology and the router architecture are presented. A throughput of more than 90% is achieved way above the 40-50% usually seen in other networks on chips.

KW - ASICs

KW - Interconnection networks

KW - Networks-on-chip

KW - Systems-on-chip

UR - https://www.scopus.com/pages/publications/46749118420

U2 - 10.1109/ICM.2006.373259

DO - 10.1109/ICM.2006.373259

M3 - Conference contribution

AN - SCOPUS:46749118420

SN - 1424407656

SN - 9781424407651

T3 - Proceedings of the International Conference on Microelectronics, ICM

SP - 28

EP - 31

BT - Proceedings of the International Conference on Microelectronics, ICM

ER -

An efficient network-on-chip architecture based on the Fat-Tree (FT) topology

Abstract

Publication series

Keywords

ASJC Scopus subject areas

UN SDGs

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Cite this