An efficient network-on-chip architecture based on the Fat-Tree (FT) topology

A novel approach for an efficient network-on-chip (NoC) using a modified Fat Tree is presented. The proposed approach totally eliminates contention and reduces the latency through an improved topology and router architecture. The adopted topology increases performance without a substantial increase in the routing cost. This is achieved by using an improved buffer-less, parameterizable router architecture. The proposed router architecture is simple to implement yet can achieve the required packet collision avoidance. Simulation results that show the level of performance achieved by both the topology and the router architecture are presented. A throughput of more than 90%, which is significantly above the 40-50% usually seen in other NoCs, is achieved. Area estimates based on logic synthesis results show that the proposed routers have significantly less area than other NoC routers. This is due to the simple routing function used and the removal of buffers.