An Efficient Methodology for On-Chip SEU Injection in Flip-Flops for Xilinx FPGAs

Field-programmable gate array (FPGA)-based single-event upset (SEU) emulation in user flip-flops is essential for reliability evaluation of mapped designs. Previous approaches to inject SEUs in user flip-flops utilized the configuration memory bits that control the set and reset settings of the flip-flops. In contrast, this paper presents a novel approach for SEU emulation in user flip-flops contents through single-frame on-chip partial reconfiguration (PR). The presented methodology exploits the inherent architectural features of the latest Xilinx FPGAs to support state initialization of flip-flops during PR. The proposed approach does not require instrumentation overhead for flip-flops and reduces the fault-injection times by orders of magnitude.