An all-digital clock recovery and data retiming circuitry for high speed NRZ data communications

Engineering

• Networks (Circuits) 100%
• Clock Recovery 100%
• Jitter Transfer 100%
• High Speed 100%
• Dynamic Behavior 50%
• Design Concept 50%
• Input Data 50%
• Static Condition 50%
• Received Data 50%
• Data Mode 50%
• Analog Filter 50%
• Phase Locked Loop 50%
• Design 50%
• Transmissions 50%
• Clock Recovery Circuit 50%
• Performance 50%
• Temperature 50%
• Support System 50%
• Amplitude 50%