TY - GEN
T1 - An all-digital clock frequency caputring circuitry for NRZ data communications
AU - Elrabaa, Muhammad E.S.
PY - 2006
Y1 - 2006
N2 - A new all-digital circuit scheme for capturing the frequency of an NRZ data stream is described. The proposed scheme is capable of retiming the output clock with the received data within two bit transitions. The absence of analog filters or other analog blocks gives it a much smaller area than conventional circuitry. Also, being fully-digital, it can be described, simulated and synthesized using hardware description languages and be ported to any technology (thus supporting system on a chip designs). Circuit operation and performance was demonstrated using a 0.13 urn, 1.2V CMOS technology and T-Spice® simulations.
AB - A new all-digital circuit scheme for capturing the frequency of an NRZ data stream is described. The proposed scheme is capable of retiming the output clock with the received data within two bit transitions. The absence of analog filters or other analog blocks gives it a much smaller area than conventional circuitry. Also, being fully-digital, it can be described, simulated and synthesized using hardware description languages and be ported to any technology (thus supporting system on a chip designs). Circuit operation and performance was demonstrated using a 0.13 urn, 1.2V CMOS technology and T-Spice® simulations.
UR - https://www.scopus.com/pages/publications/47349108492
U2 - 10.1109/ICECS.2006.379712
DO - 10.1109/ICECS.2006.379712
M3 - Conference contribution
AN - SCOPUS:47349108492
SN - 1424403952
SN - 9781424403950
T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
SP - 106
EP - 109
BT - ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
ER -