A switched capacitor multilevel inverter with self voltage balancing capability

Zeeshan Sarwer; Adil Sarwar; Mohammad Zaid; Mohd Tariq; Mohammad Ali; M. Saad Bin Arif

doi:10.1109/PEDES49360.2020.9379631

A switched capacitor multilevel inverter with self voltage balancing capability

Zeeshan Sarwer
, Adil Sarwar
, Mohammad Zaid
, Mohd Tariq
, Mohammad Ali
, M. Saad Bin Arif

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

A modified structure of a switched capacitor included multilevel inverter (SCMLI) is discussed in this paper. The proposed structure is presented with the aim to reduce the total switches. 13-level output is achieved by using 9 switches and 1 capacitor. Moreover, the additional features of the proposed structure include the self-balanced capacitor voltage, reduced total standing voltage (TSV) and output of both polarities without using an H-bridge. Simulation results showing the voltage and current waveforms for different loading conditions are included. The comparison section in the paper is present to compare the presented topology with the other inverter topologies. Results are also taken for a dynamic change in modulation index and loading conditions. MATLAB/SIMULINK is used for obtaining the simulation results, which is validated by hardware in loop implementation of the proposed topology. With the help of loss analysis, efficiency of the proposed structure is calculated. This is done by using PLECS software. The proposed topology has the maximum efficiency of 98.8 %.

Original language	English
Title of host publication	9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728156729
DOIs	https://doi.org/10.1109/PEDES49360.2020.9379631
State	Published - 16 Dec 2020
Externally published	Yes
Event	9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020 - Jaipur, India Duration: 16 Dec 2020 → 19 Dec 2020

Publication series

Name	9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020

Conference

Conference	9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020
Country/Territory	India
City	Jaipur
Period	16/12/20 → 19/12/20

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

Keywords

Multilevel Inverter
Nearest Level Control (NLC)
Total Harmonic Distortion
Total Standing Voltage

ASJC Scopus subject areas

Electrical and Electronic Engineering
Mechanical Engineering
Control and Optimization
Energy Engineering and Power Technology
Automotive Engineering

Access to Document

10.1109/PEDES49360.2020.9379631

Cite this

Sarwer, Z., Sarwar, A., Zaid, M., Tariq, M., Ali, M., & Bin Arif, M. S. (2020). A switched capacitor multilevel inverter with self voltage balancing capability. In 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020 Article 9379631 (9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PEDES49360.2020.9379631

Sarwer, Zeeshan ; Sarwar, Adil ; Zaid, Mohammad et al. / A switched capacitor multilevel inverter with self voltage balancing capability. 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020. Institute of Electrical and Electronics Engineers Inc., 2020. (9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020).

@inproceedings{79254b72209c4262be534f59feaba940,

title = "A switched capacitor multilevel inverter with self voltage balancing capability",

abstract = "A modified structure of a switched capacitor included multilevel inverter (SCMLI) is discussed in this paper. The proposed structure is presented with the aim to reduce the total switches. 13-level output is achieved by using 9 switches and 1 capacitor. Moreover, the additional features of the proposed structure include the self-balanced capacitor voltage, reduced total standing voltage (TSV) and output of both polarities without using an H-bridge. Simulation results showing the voltage and current waveforms for different loading conditions are included. The comparison section in the paper is present to compare the presented topology with the other inverter topologies. Results are also taken for a dynamic change in modulation index and loading conditions. MATLAB/SIMULINK is used for obtaining the simulation results, which is validated by hardware in loop implementation of the proposed topology. With the help of loss analysis, efficiency of the proposed structure is calculated. This is done by using PLECS software. The proposed topology has the maximum efficiency of 98.8 \%.",

keywords = "Multilevel Inverter, Nearest Level Control (NLC), Total Harmonic Distortion, Total Standing Voltage",

author = "Zeeshan Sarwer and Adil Sarwar and Mohammad Zaid and Mohd Tariq and Mohammad Ali and \{Bin Arif\}, \{M. Saad\}",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020 ; Conference date: 16-12-2020 Through 19-12-2020",

year = "2020",

month = dec,

day = "16",

doi = "10.1109/PEDES49360.2020.9379631",

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Sarwer, Z, Sarwar, A, Zaid, M, Tariq, M, Ali, M & Bin Arif, MS 2020, A switched capacitor multilevel inverter with self voltage balancing capability. in 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020., 9379631, 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020, Institute of Electrical and Electronics Engineers Inc., 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020, Jaipur, India, 16/12/20. https://doi.org/10.1109/PEDES49360.2020.9379631

A switched capacitor multilevel inverter with self voltage balancing capability. / Sarwer, Zeeshan; Sarwar, Adil; Zaid, Mohammad et al.
9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9379631 (9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A switched capacitor multilevel inverter with self voltage balancing capability

AU - Sarwer, Zeeshan

AU - Sarwar, Adil

AU - Zaid, Mohammad

AU - Tariq, Mohd

AU - Ali, Mohammad

AU - Bin Arif, M. Saad

PY - 2020/12/16

Y1 - 2020/12/16

N2 - A modified structure of a switched capacitor included multilevel inverter (SCMLI) is discussed in this paper. The proposed structure is presented with the aim to reduce the total switches. 13-level output is achieved by using 9 switches and 1 capacitor. Moreover, the additional features of the proposed structure include the self-balanced capacitor voltage, reduced total standing voltage (TSV) and output of both polarities without using an H-bridge. Simulation results showing the voltage and current waveforms for different loading conditions are included. The comparison section in the paper is present to compare the presented topology with the other inverter topologies. Results are also taken for a dynamic change in modulation index and loading conditions. MATLAB/SIMULINK is used for obtaining the simulation results, which is validated by hardware in loop implementation of the proposed topology. With the help of loss analysis, efficiency of the proposed structure is calculated. This is done by using PLECS software. The proposed topology has the maximum efficiency of 98.8 %.

AB - A modified structure of a switched capacitor included multilevel inverter (SCMLI) is discussed in this paper. The proposed structure is presented with the aim to reduce the total switches. 13-level output is achieved by using 9 switches and 1 capacitor. Moreover, the additional features of the proposed structure include the self-balanced capacitor voltage, reduced total standing voltage (TSV) and output of both polarities without using an H-bridge. Simulation results showing the voltage and current waveforms for different loading conditions are included. The comparison section in the paper is present to compare the presented topology with the other inverter topologies. Results are also taken for a dynamic change in modulation index and loading conditions. MATLAB/SIMULINK is used for obtaining the simulation results, which is validated by hardware in loop implementation of the proposed topology. With the help of loss analysis, efficiency of the proposed structure is calculated. This is done by using PLECS software. The proposed topology has the maximum efficiency of 98.8 %.

KW - Multilevel Inverter

KW - Nearest Level Control (NLC)

KW - Total Harmonic Distortion

KW - Total Standing Voltage

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T3 - 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020

BT - 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020

Y2 - 16 December 2020 through 19 December 2020

ER -

Sarwer Z, Sarwar A, Zaid M, Tariq M, Ali M, Bin Arif MS. A switched capacitor multilevel inverter with self voltage balancing capability. In 9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020. Institute of Electrical and Electronics Engineers Inc. 2020. 9379631. (9th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2020). doi: 10.1109/PEDES49360.2020.9379631

A switched capacitor multilevel inverter with self voltage balancing capability

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

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