A static test compaction technique for combinational circuits based on independent fault clustering

Yahya E. Osais; Aiman H. El-Maleh

doi:10.1109/ICECS.2003.1301757

A static test compaction technique for combinational circuits based on independent fault clustering

Yahya E. Osais, Aiman H. El-Maleh

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Testing system-on-chip involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. In this paper, a new static compaction algorithm for combinational circuits is presented. The algorithm is referred to as independent fault clustering. It is based on a new concept called test vector decomposition. Experimental results for benchmark circuits demonstrate the effectiveness of the new static compaction algorithm.

Original language	English
Title of host publication	ICECS 2003 - Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems
Pages	1316-1319
Number of pages	4
DOIs	https://doi.org/10.1109/ICECS.2003.1301757
State	Published - 2003

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume	3

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ICECS.2003.1301757

Cite this

Osais, Y. E., & El-Maleh, A. H. (2003). A static test compaction technique for combinational circuits based on independent fault clustering. In ICECS 2003 - Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems (pp. 1316-1319). Article 1301757 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 3). https://doi.org/10.1109/ICECS.2003.1301757

@inproceedings{24977c93723d49a58e56edbc40a8da79,

title = "A static test compaction technique for combinational circuits based on independent fault clustering",

abstract = "Testing system-on-chip involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. In this paper, a new static compaction algorithm for combinational circuits is presented. The algorithm is referred to as independent fault clustering. It is based on a new concept called test vector decomposition. Experimental results for benchmark circuits demonstrate the effectiveness of the new static compaction algorithm.",

author = "Osais, \{Yahya E.\} and El-Maleh, \{Aiman H.\}",

year = "2003",

doi = "10.1109/ICECS.2003.1301757",

language = "English",

isbn = "0780381637",

series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

pages = "1316--1319",

booktitle = "ICECS 2003 - Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems",

}

Osais, YE & El-Maleh, AH 2003, A static test compaction technique for combinational circuits based on independent fault clustering. in ICECS 2003 - Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems., 1301757, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 3, pp. 1316-1319. https://doi.org/10.1109/ICECS.2003.1301757

A static test compaction technique for combinational circuits based on independent fault clustering. / Osais, Yahya E.; El-Maleh, Aiman H.
ICECS 2003 - Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems. 2003. p. 1316-1319 1301757 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A static test compaction technique for combinational circuits based on independent fault clustering

AU - Osais, Yahya E.

AU - El-Maleh, Aiman H.

PY - 2003

Y1 - 2003

N2 - Testing system-on-chip involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. In this paper, a new static compaction algorithm for combinational circuits is presented. The algorithm is referred to as independent fault clustering. It is based on a new concept called test vector decomposition. Experimental results for benchmark circuits demonstrate the effectiveness of the new static compaction algorithm.

AB - Testing system-on-chip involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. In this paper, a new static compaction algorithm for combinational circuits is presented. The algorithm is referred to as independent fault clustering. It is based on a new concept called test vector decomposition. Experimental results for benchmark circuits demonstrate the effectiveness of the new static compaction algorithm.

UR - https://www.scopus.com/pages/publications/77956050229

U2 - 10.1109/ICECS.2003.1301757

DO - 10.1109/ICECS.2003.1301757

M3 - Conference contribution

AN - SCOPUS:77956050229

SN - 0780381637

SN - 9780780381636

T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

SP - 1316

EP - 1319

BT - ICECS 2003 - Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems

ER -

Osais YE , El-Maleh AH. A static test compaction technique for combinational circuits based on independent fault clustering. In ICECS 2003 - Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems. 2003. p. 1316-1319. 1301757. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). doi: 10.1109/ICECS.2003.1301757

A static test compaction technique for combinational circuits based on independent fault clustering

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ASJC Scopus subject areas

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