A state machine synthesizer with Weinberger arrays

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The authors describe the development of a digital circuit synthesis program. The program accepts the transition table of a state machine and returns equations for an implementation that assume a sum-of-product next-state and output functions. From the equations for the next-state and output functions, an nMOS VLSI layout for a Weinberger array (WA) is generated. D flip-flops are assumed for memory elements. Using this tool, tedious manual calculations can be avoided and layouts are generated automatically from state table descriptions.

Original languageEnglish
Title of host publicationIEEE Pacific Rim Conference on Communications, Computers and Signal Processing. Conference Proceedings
Editors Anon
PublisherPubl by IEEE
Pages753-756
Number of pages4
ISBN (Print)0879426381
StatePublished - 1991
Externally publishedYes

Publication series

NameIEEE Pacific Rim Conference on Communications, Computers and Signal Processing. Conference Proceedings

ASJC Scopus subject areas

  • Signal Processing
  • Computer Networks and Communications

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