TY - GEN
T1 - A SNDR BIST for ∑Δ analogue-to-digital converters
AU - Rolíndez, Luis
AU - Mir, Salvador
AU - Bounceur, Ahcène
AU - Carbonéro, Jean Louis
PY - 2006
Y1 - 2006
N2 - The test of high resolution Sigma-Delta Analogue-to-Digital Converters (∑Δ ADCs) is a costly task due to its high resolution and the large number of samples required. In this paper, we propose a Built-in Self-Test (BIST) technique for the test of SNDR (Signal-to-Noise plus Distortion Ratio) in ∑Δ ADCs. The technique, mostly digital, uses a binary stream as test stimulus and carries out a sine-wave fitting algorithm to analyse the output response. Both the test signal generation and the output response analysis are performed on-chip, taking advantage of the digital resources already present in a ∑Δ ADC. Simulations results show the capability of this technique to obtain measures of the SNDR for a 16-bit audio ∑Δ ADC.
AB - The test of high resolution Sigma-Delta Analogue-to-Digital Converters (∑Δ ADCs) is a costly task due to its high resolution and the large number of samples required. In this paper, we propose a Built-in Self-Test (BIST) technique for the test of SNDR (Signal-to-Noise plus Distortion Ratio) in ∑Δ ADCs. The technique, mostly digital, uses a binary stream as test stimulus and carries out a sine-wave fitting algorithm to analyse the output response. Both the test signal generation and the output response analysis are performed on-chip, taking advantage of the digital resources already present in a ∑Δ ADC. Simulations results show the capability of this technique to obtain measures of the SNDR for a 16-bit audio ∑Δ ADC.
UR - https://www.scopus.com/pages/publications/33751095955
U2 - 10.1109/VTS.2006.12
DO - 10.1109/VTS.2006.12
M3 - Conference contribution
AN - SCOPUS:33751095955
SN - 0769525148
SN - 9780769525143
T3 - Proceedings of the IEEE VLSI Test Symposium
SP - 314
EP - 319
BT - Proceedings - 24th IEEE VLSI Test Symposium
T2 - 24th IEEE VLSI Test Symposium
Y2 - 30 April 2006 through 4 May 2006
ER -