A sequential circuit fault tolerance technique with enhanced area and power

Aiman H. El-Maleh

doi:10.1109/ISSPIT.2015.7394348

A sequential circuit fault tolerance technique with enhanced area and power

Aiman H. El-Maleh^*

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Increasing rates of soft errors at the nanometer scale require effective fault tolerant solutions. Recently, a finite state machine (FSM) based fault tolerance technique for sequential circuits has been proposed. The technique is based on protecting few states with high probability of occurrence by adding equivalent redundant states. The resulting state assignment solution satisfies the fault tolerance requirements but has no control on the area or power of synthesized sequential circuits. In this work, we propose an algorithm that starts with a given state assignment solution targeting the optimization of power and generates a state assignment solution that preserves the original assignment and satisfies the fault tolerance requirements. Experimental results demonstrate the effectiveness of the proposed algorithm in significantly reducing the area and power of synthesized sequential circuits while enhancing their fault tolerance.

Original language	English
Title of host publication	2015 IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	301-304
Number of pages	4
ISBN (Electronic)	9781509004805
DOIs	https://doi.org/10.1109/ISSPIT.2015.7394348
State	Published - 28 Jan 2016

Publication series

Name	2015 IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2015

Bibliographical note

Funding Information:
This work is supported by King Fahd University of Petroleum and Minerals under Project# IN131014. The author acknowledges Mr. Ayed Al-Qahtani for his help in the implementation of this work.

Publisher Copyright:
© 2015 IEEE.

ASJC Scopus subject areas

Signal Processing

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10.1109/ISSPIT.2015.7394348

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El-Maleh, A. H. (2016). A sequential circuit fault tolerance technique with enhanced area and power. In 2015 IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2015 (pp. 301-304). Article 7394348 (2015 IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSPIT.2015.7394348

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abstract = "Increasing rates of soft errors at the nanometer scale require effective fault tolerant solutions. Recently, a finite state machine (FSM) based fault tolerance technique for sequential circuits has been proposed. The technique is based on protecting few states with high probability of occurrence by adding equivalent redundant states. The resulting state assignment solution satisfies the fault tolerance requirements but has no control on the area or power of synthesized sequential circuits. In this work, we propose an algorithm that starts with a given state assignment solution targeting the optimization of power and generates a state assignment solution that preserves the original assignment and satisfies the fault tolerance requirements. Experimental results demonstrate the effectiveness of the proposed algorithm in significantly reducing the area and power of synthesized sequential circuits while enhancing their fault tolerance.",

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El-Maleh, AH 2016, A sequential circuit fault tolerance technique with enhanced area and power. in 2015 IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2015., 7394348, 2015 IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2015, Institute of Electrical and Electronics Engineers Inc., pp. 301-304. https://doi.org/10.1109/ISSPIT.2015.7394348

A sequential circuit fault tolerance technique with enhanced area and power. / El-Maleh, Aiman H.
2015 IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2015. Institute of Electrical and Electronics Engineers Inc., 2016. p. 301-304 7394348 (2015 IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Increasing rates of soft errors at the nanometer scale require effective fault tolerant solutions. Recently, a finite state machine (FSM) based fault tolerance technique for sequential circuits has been proposed. The technique is based on protecting few states with high probability of occurrence by adding equivalent redundant states. The resulting state assignment solution satisfies the fault tolerance requirements but has no control on the area or power of synthesized sequential circuits. In this work, we propose an algorithm that starts with a given state assignment solution targeting the optimization of power and generates a state assignment solution that preserves the original assignment and satisfies the fault tolerance requirements. Experimental results demonstrate the effectiveness of the proposed algorithm in significantly reducing the area and power of synthesized sequential circuits while enhancing their fault tolerance.

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El-Maleh AH. A sequential circuit fault tolerance technique with enhanced area and power. In 2015 IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2015. Institute of Electrical and Electronics Engineers Inc. 2016. p. 301-304. 7394348. (2015 IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2015). doi: 10.1109/ISSPIT.2015.7394348

A sequential circuit fault tolerance technique with enhanced area and power

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