Abstract
A new scheme of test data compression/decompression, namely coding of even bits marking and selective output inversion, is presented. It first uses a special kind of codewords, odd bits of which are used to represent the length of runs and even bits of which are used to represent whether the codewords finish. The characteristic of the codewords make the structure of decompressor simple. It then introduces a structure of selective output inversion to increase the probability of 0s. This scheme can obtain a better compression ratio than some already known schemes, but it only needs a very low hardware overhead. The performance of the scheme is experimentally confirmed on the larger examples of the ISCAS89 benchmark circuits.
Original language | English |
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Pages (from-to) | 969-977 |
Number of pages | 9 |
Journal | Computers and Electrical Engineering |
Volume | 36 |
Issue number | 5 |
DOIs | |
State | Published - Sep 2010 |
Bibliographical note
Funding Information:The authors would like to thank Prof. Nur A. Touba, who is at the Department of Electrical and Computer Engineering, University of Texas at Austin, and Prof. Krishnendu Chakrabarty, who is at the Department of Electrical and Computer Engineering, Duke University, for their suggestions to revise this paper. This work is supported in part by the National Natural Science Foundation of China (Nos. 90407008 and 60633060), and Scientific Research Foundation for Excellent Youth Scholars of high institutions in Anhui Province (No. 2010SQRL110).
Keywords
- Stimulus compression
- System-on-a-chip (SoC)
- Test
- Test data compression
- Test vector
ASJC Scopus subject areas
- Control and Systems Engineering
- General Computer Science
- Electrical and Electronic Engineering