TY - GEN
T1 - A reconfigurable Satlin/Sigmoid/Gaussian/Triangular Basis functions computation circuit
AU - Abuelma'ati, Muhammad Taher
AU - Shwehneh, Abdullah
PY - 2006
Y1 - 2006
N2 - A CMOS Satlin/Sigmoid/Gaussian/Triangular Basis functions computation circuit suitable for analog neural networks is proposed. The circuit can be configured to realize any of the four functions. The circuit can approximate these functions with relative root-mean-square error less than 1%. It is shown that the center, width, and peak amplitude of the dc transfer characteristic can be independently controlled. HSPICE simulation results using 0.18um CMOS process model parameters of TSMC technology are included.
AB - A CMOS Satlin/Sigmoid/Gaussian/Triangular Basis functions computation circuit suitable for analog neural networks is proposed. The circuit can be configured to realize any of the four functions. The circuit can approximate these functions with relative root-mean-square error less than 1%. It is shown that the center, width, and peak amplitude of the dc transfer characteristic can be independently controlled. HSPICE simulation results using 0.18um CMOS process model parameters of TSMC technology are included.
KW - Analog neural networks
KW - CMOS circuits
KW - Computational circuits
UR - https://www.scopus.com/pages/publications/50249105193
U2 - 10.1109/APCCAS.2006.342350
DO - 10.1109/APCCAS.2006.342350
M3 - Conference contribution
AN - SCOPUS:50249105193
SN - 1424403871
SN - 9781424403875
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 1172
EP - 1175
BT - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
ER -