A power-efficient dynamic-time current mode comparator

This paper presents a power-efficient dynamic-time current comparator for current mode signal processing. The proposed circuit utilizes a switched feedback-based inverter and a clock-shaping circuit. The switched feedback-based inverter can detect the polarity of the sensed current from the current subtraction circuit. While the clock-shaping circuit can manage the power consumption. Since the proposed current comparator exhibits a high sensitivity to ultra-low input current with a low input offset, it can be exploited in a current mode successive-approximation-register analog-to-digital converters for a wide range of wearable applications. Moreover, a design methodology for an efficient and robust current comparator is presented. The circuit is designed and simulated in TSMC 0.13 µm CMOS technology, and occupies a silicon area of 7834 µm². The proposed current comparator consumes a power of 14 µW with a single power supply of 1.2 V. It provides a resolution of 2 nA, and a delay of 4.6 ns. Moreover, the post-layout simulation results indicate a good agreement compared to the prior art.