A platform for LDPC code design and performance evaluation

In this paper, the design and implementation aspects of a novel platform for aiding in the construction and performance evaluation of Low Density Parity Check (LDPC) codes is presented. The proposed platform is capable of performing two major tasks: (1) parallel simulation for evaluating LDPC codes performance in a very short time compared to existing LDPC code simulation tools, and (2) displaying the internal state of LDPC decoder during decoding iterations using a graphical user interface (GUI) which allows the LDPC code designer to visually inspect the weak areas. The existing LDPC code simulation tools take a long time in evaluating the performance of a specific LDPC code design, particularly in high SNR regions. This is due to the large number of computations required. This problem is overcome by developing a parallel protocol to distribute the computations among processing nodes in a TCP/IP network. As indicated by experimental results, the proposed simulation platform is scalable with the number of processing nodes. Another practical advantage of the proposed system is that it does not need dedicated processors; rather, it can utilize idle times of processing nodes in a network and work transparently to any node user. Furthermore, network daemons are adopted in order to detect and utilize network nodes even if they are in the log-off state. The second major task of the proposed platform is to analyze LDPC code performance and inspect weak areas in a given LDPC code design. To meet this objective, a method is proposed to graphically display the behavior of the LDPC decoder through the decoding iterations. This is then exploited to detect weak constructions (such as failure "trapping loops") that prevent the decoder from continuously improving the bit error performance.