TY - GEN
T1 - A novel flash erase EEPROM memory cell with reversed poly roles
AU - Amin, Alaaeldin A.M.
PY - 1992
Y1 - 1992
N2 - A novel structure for a flash EEPROM memory cell is described. The structure employs the first poly as a control gate, while the second poly is used as the floating gate. Such a reversed structure allows the floating gate to overlap both the source and drain even with a merged transistor memory cell structure. Erasing can thus be performed independently at the source junction while programming is performed at the drain junction. This allows the independent optimization of each of the two junctions to satisfy the conflicting program and erase requirements. In addition, an alternative cell structure with a third poly erase electrode is made possible by the reversed poly roles.
AB - A novel structure for a flash EEPROM memory cell is described. The structure employs the first poly as a control gate, while the second poly is used as the floating gate. Such a reversed structure allows the floating gate to overlap both the source and drain even with a merged transistor memory cell structure. Erasing can thus be performed independently at the source junction while programming is performed at the drain junction. This allows the independent optimization of each of the two junctions to satisfy the conflicting program and erase requirements. In addition, an alternative cell structure with a third poly erase electrode is made possible by the reversed poly roles.
UR - https://www.scopus.com/pages/publications/0026737136
M3 - Conference contribution
AN - SCOPUS:0026737136
SN - 0879426551
T3 - 6th Mediterranean Electrotechnical Conference
SP - 311
EP - 314
BT - 6th Mediterranean Electrotechnical Conference
PB - Publ by IEEE
T2 - Proceedings of the 6th Mediterranean Electrotechnical Conference - Melecon '91
Y2 - 22 May 1991 through 24 May 1991
ER -