A novel flash erase EEPROM memory cell with asperities aided erase

Alaaeldin A.M. Amin

A novel flash erase EEPROM memory cell with asperities aided erase

Alaaeldin A.M. Amin^*

^*Corresponding author for this work

King Fahd University of Petroleum & Minerals

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A novel²flash erase EEPROM, memory cell structure is presented. The cell uses triple poly layers and two independent N⁺implants. The first poly is used as the control gate, the second poly as the floating gate and the third poly as arc erase electrode. Cell programminng is avalanche injection of hot electrons into the floating gate, while erasure is performed by asperities-aided Fowler Nordheim tunneling of electrons. Asperities introduced at the top surface of the floating poly gate allow using thicker interpoly oxide at lower erase voltage and less than 0.1 second erase time.

Original language	English
Title of host publication	ESSDERC 1990 - 20th European Solid State Device Research Conference
Editors	W. Eccleston, P. J. Rosser
Publisher	IEEE Computer Society
Pages	177-180
Number of pages	4
ISBN (Electronic)	0750300655
State	Published - 1990

Publication series

Name	European Solid-State Device Research Conference
ISSN (Print)	1930-8876

Bibliographical note

Publisher Copyright:
© 1990 IOP Publishing Ltd.

ASJC Scopus subject areas

Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Cite this

@inproceedings{e06d956e322f48b5bc634db7872379ed,

title = "A novel flash erase EEPROM memory cell with asperities aided erase",

abstract = "A novel2flash erase EEPROM, memory cell structure is presented. The cell uses triple poly layers and two independent N+implants. The first poly is used as the control gate, the second poly as the floating gate and the third poly as arc erase electrode. Cell programminng is avalanche injection of hot electrons into the floating gate, while erasure is performed by asperities-aided Fowler Nordheim tunneling of electrons. Asperities introduced at the top surface of the floating poly gate allow using thicker interpoly oxide at lower erase voltage and less than 0.1 second erase time.",

author = "Amin, \{Alaaeldin A.M.\}",

note = "Publisher Copyright: {\textcopyright} 1990 IOP Publishing Ltd.",

year = "1990",

language = "English",

series = "European Solid-State Device Research Conference",

publisher = "IEEE Computer Society",

pages = "177--180",

editor = "W. Eccleston and Rosser, \{P. J.\}",

booktitle = "ESSDERC 1990 - 20th European Solid State Device Research Conference",

address = "United States",

}

A novel flash erase EEPROM memory cell with asperities aided erase. / Amin, Alaaeldin A.M.
ESSDERC 1990 - 20th European Solid State Device Research Conference. ed. / W. Eccleston; P. J. Rosser. IEEE Computer Society, 1990. p. 177-180 5436441 (European Solid-State Device Research Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A novel flash erase EEPROM memory cell with asperities aided erase

AU - Amin, Alaaeldin A.M.

PY - 1990

Y1 - 1990

N2 - A novel2flash erase EEPROM, memory cell structure is presented. The cell uses triple poly layers and two independent N+implants. The first poly is used as the control gate, the second poly as the floating gate and the third poly as arc erase electrode. Cell programminng is avalanche injection of hot electrons into the floating gate, while erasure is performed by asperities-aided Fowler Nordheim tunneling of electrons. Asperities introduced at the top surface of the floating poly gate allow using thicker interpoly oxide at lower erase voltage and less than 0.1 second erase time.

AB - A novel2flash erase EEPROM, memory cell structure is presented. The cell uses triple poly layers and two independent N+implants. The first poly is used as the control gate, the second poly as the floating gate and the third poly as arc erase electrode. Cell programminng is avalanche injection of hot electrons into the floating gate, while erasure is performed by asperities-aided Fowler Nordheim tunneling of electrons. Asperities introduced at the top surface of the floating poly gate allow using thicker interpoly oxide at lower erase voltage and less than 0.1 second erase time.

UR - https://www.scopus.com/pages/publications/84908006634

M3 - Conference contribution

AN - SCOPUS:84908006634

T3 - European Solid-State Device Research Conference

SP - 177

EP - 180

BT - ESSDERC 1990 - 20th European Solid State Device Research Conference

A2 - Eccleston, W.

A2 - Rosser, P. J.

PB - IEEE Computer Society

ER -

A novel flash erase EEPROM memory cell with asperities aided erase

Abstract

Publication series

Bibliographical note

ASJC Scopus subject areas

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Cite this