TY - GEN
T1 - A novel current-mode ultra low power analog CMOS four quadrant multiplier
AU - Al-Absi, Munir Ahmad
AU - Hussein, Alaa
AU - Abuelma'atti, Muhammad Taher
PY - 2012
Y1 - 2012
N2 - A novel CMOS current mode analog multiplier is presented. The design is based on using MOSFET operating in subthreshold region to achieve ultra low power dissipation. The circuit is operated from ± 0.75V DC supply. The proposed circuit has been simulated using Tanner in 0.35μm TSMC CMOS process. Simulation results show that the total power dissipation is 2.3μW, total harmonic distortion is 0.7% , maximum linearity error is 0.3% and the bandwidth is 2.8MHz.
AB - A novel CMOS current mode analog multiplier is presented. The design is based on using MOSFET operating in subthreshold region to achieve ultra low power dissipation. The circuit is operated from ± 0.75V DC supply. The proposed circuit has been simulated using Tanner in 0.35μm TSMC CMOS process. Simulation results show that the total power dissipation is 2.3μW, total harmonic distortion is 0.7% , maximum linearity error is 0.3% and the bandwidth is 2.8MHz.
KW - Translinear principle
KW - current mode
KW - four quadrant analog multiplier
UR - https://www.scopus.com/pages/publications/84867267017
U2 - 10.1109/ICCCE.2012.6271143
DO - 10.1109/ICCCE.2012.6271143
M3 - Conference contribution
AN - SCOPUS:84867267017
SN - 9781467304788
T3 - 2012 International Conference on Computer and Communication Engineering, ICCCE 2012
SP - 13
EP - 17
BT - 2012 International Conference on Computer and Communication Engineering, ICCCE 2012
ER -