A new static differential CMOS logic with superior low power performance

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4 Scopus citations

Abstract

A new differential static CMOS logic (DSCL) family is devised. The new circuit is fully static, making it simple to design. The circuit topology of the DSCL and its operation is explained. Its performance in terms of delay, power, and area is compared to that of conventional static differential logic and dynamic differential logic. Spice simulations using a 0.18 μm technology with a power supply of 1.W was utilized to evaluate the performance of the three circuits. Two different sets of simulations were carried out; one with equal input capacitances of all circuits and another with equal circuit delays. For each design, all circuits were optimized for minimum delay. It is shown that at equal input capacitance, the DSCL achieved 40% less delay than the DCVSL at one third the power. Also, at equal delay, the DSCL achieved 20% of the power dissipation of the DCVSL and 78% of the DDCVSL making it the most energy-efficient among the three circuits.

Original languageEnglish
Title of host publicationICECS 2003 - Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems
Pages810-813
Number of pages4
DOIs
StatePublished - 2003

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume2

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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