A New Seven-Level Inverter Topology with Reduced Switch Number

Marif Daula Siddique; Atif Iqbal; Mohammed Al-Hitmi

doi:10.1109/IECON43393.2020.9255108

A New Seven-Level Inverter Topology with Reduced Switch Number

Marif Daula Siddique
, Atif Iqbal
, Mohammed Al-Hitmi

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper aims to improve the power and voltage quality of a new multilevel inverter which contains a smaller number of switches in the specified voltage levels. The single phase of the proposed inverter includes 8 electronic power devices with three dc voltage sources for the seven-level waveforms. Selective harmonic elimination (SHE) technique has been used for the dominant harmonic elimination. The results of the proposed structure with traditional topologies and similar topologies show that, in terms of switch number, driver number, and the total blocking voltage, the proposed structure was superior to the previous versions. This topology is studied by simulations in the environment of PLECS.

Original language	English
Title of host publication	Proceedings - IECON 2020
Subtitle of host publication	46th Annual Conference of the IEEE Industrial Electronics Society
Pages	3285-3290
Number of pages	6
ISBN (Electronic)	9781728154145
DOIs	https://doi.org/10.1109/IECON43393.2020.9255108
State	Published - 18 Oct 2020

Publication series

Name	IECON Proceedings (Industrial Electronics Conference)
Volume	2020-October

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

Keywords

multilevel inverter
power switches
reduced switched count
SHEPWM

ASJC Scopus subject areas

Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/IECON43393.2020.9255108

Cite this

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title = "A New Seven-Level Inverter Topology with Reduced Switch Number",

abstract = "This paper aims to improve the power and voltage quality of a new multilevel inverter which contains a smaller number of switches in the specified voltage levels. The single phase of the proposed inverter includes 8 electronic power devices with three dc voltage sources for the seven-level waveforms. Selective harmonic elimination (SHE) technique has been used for the dominant harmonic elimination. The results of the proposed structure with traditional topologies and similar topologies show that, in terms of switch number, driver number, and the total blocking voltage, the proposed structure was superior to the previous versions. This topology is studied by simulations in the environment of PLECS.",

keywords = "multilevel inverter, power switches, reduced switched count, SHEPWM",

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doi = "10.1109/IECON43393.2020.9255108",

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A New Seven-Level Inverter Topology with Reduced Switch Number. / Siddique, Marif Daula; Iqbal, Atif; Al-Hitmi, Mohammed.
Proceedings - IECON 2020: 46th Annual Conference of the IEEE Industrial Electronics Society. 2020. p. 3285-3290 9255108 (IECON Proceedings (Industrial Electronics Conference); Vol. 2020-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Iqbal, Atif

AU - Al-Hitmi, Mohammed

PY - 2020/10/18

Y1 - 2020/10/18

N2 - This paper aims to improve the power and voltage quality of a new multilevel inverter which contains a smaller number of switches in the specified voltage levels. The single phase of the proposed inverter includes 8 electronic power devices with three dc voltage sources for the seven-level waveforms. Selective harmonic elimination (SHE) technique has been used for the dominant harmonic elimination. The results of the proposed structure with traditional topologies and similar topologies show that, in terms of switch number, driver number, and the total blocking voltage, the proposed structure was superior to the previous versions. This topology is studied by simulations in the environment of PLECS.

AB - This paper aims to improve the power and voltage quality of a new multilevel inverter which contains a smaller number of switches in the specified voltage levels. The single phase of the proposed inverter includes 8 electronic power devices with three dc voltage sources for the seven-level waveforms. Selective harmonic elimination (SHE) technique has been used for the dominant harmonic elimination. The results of the proposed structure with traditional topologies and similar topologies show that, in terms of switch number, driver number, and the total blocking voltage, the proposed structure was superior to the previous versions. This topology is studied by simulations in the environment of PLECS.

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KW - power switches

KW - reduced switched count

KW - SHEPWM

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ER -

A New Seven-Level Inverter Topology with Reduced Switch Number

Abstract

Publication series

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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