A new scheme of test data compression based on equal-run-length coding (ERLC)

Wenfa Zhan; Aiman El-Maleh

doi:10.1016/j.vlsi.2011.05.001

A new scheme of test data compression based on equal-run-length coding (ERLC)

Wenfa Zhan^*, Aiman El-Maleh

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

24 Scopus citations

Abstract

A new scheme of test data compression based on run-length, namely equal-run-length coding (ERLC) is presented. It is based on both types of runs of 0s and 1s and explores the relationship between two consecutive runs. It uses a shorter codeword to represent the whole second run of two equal length consecutive runs. A scheme for filling the don't-care bits is proposed to maximize the number of consecutive equal-length runs. Compared with other already known schemes, the proposed scheme achieves higher compression ratio with low area overhead. The merits of the proposed algorithm are experimentally verified on the larger examples of the ISCAS89 benchmark circuits.

Original language	English
Pages (from-to)	91-98
Number of pages	8
Journal	Integration, the VLSI Journal
Volume	45
Issue number	1
DOIs	https://doi.org/10.1016/j.vlsi.2011.05.001
State	Published - Jan 2012

Bibliographical note

Funding Information:
This work is supported by Anhui Provincial Natural Science Foundation (no. 10040606Q42 ) and Natural Science Foundation of Province College of Anhui under (no. KJ2011A198 ). Dr. El-Maleh acknowledges support from King Fahd University of Petroleum and minerals.

Keywords

Built-in Self-Test
Coding
Test compression
VLSI test

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1016/j.vlsi.2011.05.001

Cite this

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A new scheme of test data compression based on equal-run-length coding (ERLC)

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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