A New Floating and Tunable Capacitance Multiplier with Large Multiplication Factor

Munir Ahmad Al-Absi*, Abdulaziz Ahmed Al-Khulaifi

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

35 Scopus citations

Abstract

This paper presents a CMOS floating and tunable capacitance multiplier with a very large multiplication factor. The proposed design uses CCII and OTAs designed using MOSFETs biased in subthreshold region to provide low power consumption and high multiplication factor. TANNER TSPICE simulation tool is used to confirm the functionality of the design in 0.18μm TSMC CMOS technology. The circuit is powered using ±0.75V DC supply voltage. Simulation results indicate that the maximum multiplication factor is 3600 and the maximum error is 8.6%.

Original languageEnglish
Article number8808856
Pages (from-to)120076-120081
Number of pages6
JournalIEEE Access
Volume7
DOIs
StatePublished - 2019

Bibliographical note

Publisher Copyright:
© 2013 IEEE.

Keywords

  • Impedance multiplier
  • biomedical circuits
  • filters
  • high multiplication factor
  • tunable

ASJC Scopus subject areas

  • General Computer Science
  • General Materials Science
  • General Engineering

Fingerprint

Dive into the research topics of 'A New Floating and Tunable Capacitance Multiplier with Large Multiplication Factor'. Together they form a unique fingerprint.

Cite this