A New CMOS Controllable Impedance Multiplier with Large Multiplication Factor

Munir A. Al-Absi*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

This paper presents a new compact controllable impedance multiplier using CMOS technology. The design is based on the use of the translinear principle using MOSFETs in subthreshold region. The value of the impedance will be controlled using the bias currents only. The impedance can be scaled up and down as required. The functionality of the proposed design was confirmed by simulation using BSIM3V3 MOS model in Tanner Tspice 0.18 μm TSMC CMOS process technology. Simulation results indicate that the proposed design is functioning properly with a tunable multiplication factor from 0.1- to 100-fold. Applications of the proposed multiplier in the design of low pass and high pass filters are also included.

Original languageEnglish
Article number4274791
JournalActive and Passive Electronic Components
Volume2017
DOIs
StatePublished - 2017

Bibliographical note

Publisher Copyright:
© 2017 Munir A. Al-Absi.

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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