TY - GEN
T1 - A massively parallel RNS architecture
AU - Elleithy, Khaled M.
AU - Bayoumi, Magdy A.
PY - 1991
Y1 - 1991
N2 - Parallelism on the algorithmic, architectural, and arithmetic levels is exploited in the design of a residue number system (RNS) based architecture. The architecture is based on modulo processors. Each modulo processor is implemented by a two-dimensional systolic array composed of very simple cells. The decoding stage is implemented using a two-dimensional array. The decoding bottleneck is eliminated. The whole architecture is pipelined, which leads to a high throughput rate. High speed algorithms for modulo addition, modulo multiplication, and RNS decoding are presented.
AB - Parallelism on the algorithmic, architectural, and arithmetic levels is exploited in the design of a residue number system (RNS) based architecture. The architecture is based on modulo processors. Each modulo processor is implemented by a two-dimensional systolic array composed of very simple cells. The decoding stage is implemented using a two-dimensional array. The decoding bottleneck is eliminated. The whole architecture is pipelined, which leads to a high throughput rate. High speed algorithms for modulo addition, modulo multiplication, and RNS decoding are presented.
UR - http://www.scopus.com/inward/record.url?scp=0026264235&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0026264235
SN - 0818624701
T3 - Conference Record - Asilomar Conference on Circuits, Systems & Computers
SP - 408
EP - 412
BT - Conference Record - Asilomar Conference on Circuits, Systems & Computers
PB - Publ by Maple Press, Inc
ER -