TY - GEN
T1 - A hybrid test compression technique for efficient testing of Systems-on-a-Chip
AU - El-Maleh, Aiman H.
PY - 2003
Y1 - 2003
N2 - One of the major challenges in testing a System-on-a-Chip (SOC) is dealing with the large test data size. To reduce the volume of test data, several efficient test data compression techniques have been recently proposed. In this paper, we propose hybrid test compression techniques that combine the Geometric-Primitives-Based compression technique with the frequency-directed run-length (FDR) and extended frequencydirected run-length (EFDR) coding techniques. Based on experimental results, we demonstrate the effectiveness of the proposed hybrid compression techniques in increasing the test data compression ratios over those obtained by the Geometric- Primitives-Based compression technique.
AB - One of the major challenges in testing a System-on-a-Chip (SOC) is dealing with the large test data size. To reduce the volume of test data, several efficient test data compression techniques have been recently proposed. In this paper, we propose hybrid test compression techniques that combine the Geometric-Primitives-Based compression technique with the frequency-directed run-length (FDR) and extended frequencydirected run-length (EFDR) coding techniques. Based on experimental results, we demonstrate the effectiveness of the proposed hybrid compression techniques in increasing the test data compression ratios over those obtained by the Geometric- Primitives-Based compression technique.
UR - https://www.scopus.com/pages/publications/35248898681
U2 - 10.1109/ICECS.2003.1301856
DO - 10.1109/ICECS.2003.1301856
M3 - Conference contribution
AN - SCOPUS:35248898681
SN - 0780381637
SN - 9780780381636
T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
SP - 599
EP - 602
BT - ICECS 2003 - Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems
ER -