TY - GEN
T1 - A high-throughput network-on-chip architecture for systems-on-chip interconnect
AU - Bouhraoua, A.
AU - Elrabaa, M. E.
PY - 2006
Y1 - 2006
N2 - A buffer-less, contention-free, Network-on-Chip architecture based on a modified Fat Tree is proposed. Simulations results show that the proposed architecture achieves maximum throughput (> 90%) way above the 40-50% seen in conventional Fat Trees. Contention is eliminated and latency is reduced through an improved topology and router architecture. Area of the network is kept to a minimum by pushing the buffers to the edge of the network at the client interface. Simulation results show that the required number of buffers at the client interface is a fraction of the theoretical maximum. This means that the actual number of buffers can be tailored to suit a class of applications running on a specific platform.
AB - A buffer-less, contention-free, Network-on-Chip architecture based on a modified Fat Tree is proposed. Simulations results show that the proposed architecture achieves maximum throughput (> 90%) way above the 40-50% seen in conventional Fat Trees. Contention is eliminated and latency is reduced through an improved topology and router architecture. Area of the network is kept to a minimum by pushing the buffers to the edge of the network at the client interface. Simulation results show that the required number of buffers at the client interface is a fraction of the theoretical maximum. This means that the actual number of buffers can be tailored to suit a class of applications running on a specific platform.
UR - https://www.scopus.com/pages/publications/50049113994
U2 - 10.1109/ISSOC.2006.321984
DO - 10.1109/ISSOC.2006.321984
M3 - Conference contribution
AN - SCOPUS:50049113994
SN - 1424406226
SN - 9781424406227
T3 - 2006 International Symposium on System-on-Chip, SOC
BT - 2006 International Symposium on System-on-Chip, SOC
ER -