A generic M-phase, N-stage folded cross-coupled CMOS rectifier architecture for low-power RF energy harvesting

This paper presents a generic, parameterized M -phase, N -stage folded cross-coupled CMOS rectifier architecture for low-power RF energy harvesting. A simulation-driven, lookup-table (LUT)–based rectifier and impedance-matching co-design framework is introduced. The framework explicitly incorporates layout, package, and PCB parasitic elements, such as bond-wire inductance, pad capacitance, and PCB trace effects, into the input matching network design to ensure robust impedance matching and efficient power transfer. The folded multi-phase organization enables compact implementation through phase-interleaved charge transfer. As a result, power conversion efficiency (PCE), dynamic range, and output stability are improved across scalable phase and stage combinations. A representative case study is selected based on a target output voltage of approximately 2 V, which is suitable for powering modern low-power IoT and biomedical circuits without additional DC–DC conversion. Post-layout (PEX) simulations are performed in 180-nm CMOS technology at 920 MHz with a 100 kΩ load. A four-phase, four-stage implementation achieves a peak PCE of 77.1% at −12.5 dBm, with a dynamic range exceeding 25 dB and a sensitivity of −16.8 dBm. The rectifier delivers approximately 2.1 V with 1.8 mV_pp ripple using a 2 pF load capacitor. Monte Carlo and process–voltage–temperature simulations confirm robust operation. Benchmarking using established figures of merit demonstrates competitive efficiency and scalability compared with prior art.