Abstract
This paper presents a novel topology for fault-tolerant multilevel inverters featuring three sources with improved performance in post-fault conditions. The conventional three-source topology has a total of eight switches, and anyone switch's failure severely impacts output voltage and harmonics. A fault analysis has been carried out for the conventional three-source topology, which has led to the development of a novel fault-tolerant MLI. For the proposed fault-tolerant topology, the number of levels and output voltage improve in the post-fault conditions for different modes of operation. For the proposed topology, a detailed fault analysis, along with the power quality assessment that has been carried out for open-circuit faults to every switch, has been provided in this paper. Finally, the simulation results have been provided to validate the proposed topology.
| Original language | English |
|---|---|
| Journal | Proceedings of the International Conference on Power Electronics, Drives, and Energy Systems for Industrial Growth, PEDES |
| Issue number | 2024 |
| DOIs | |
| State | Published - 2024 |
| Event | 11th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2024 - Mangalore, India Duration: 18 Dec 2024 → 21 Dec 2024 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
Keywords
- fault-tolerant
- multilevel inverter
- reduced switch count
- Three-source configuration
ASJC Scopus subject areas
- Energy Engineering and Power Technology
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality
- Mechanical Engineering
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