Abstract
This paper presents an efficient and novel method for sequential learning of implications, invalid states, and tied gates. It can handle real industrial circuits, with multiple clock domains and partial setheset. The application of this method to improve the efficiency of sequential ATPG is also demonstrated by achieving higher fault coverages and lower test generation times.
| Original language | English |
|---|---|
| Title of host publication | Proceedings 1998 - Design and Automation Conference, DAC 1998 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 625-631 |
| Number of pages | 7 |
| ISBN (Print) | 078034409X |
| State | Published - 1998 |
| Externally published | Yes |
Publication series
| Name | Proceedings - Design Automation Conference |
|---|---|
| ISSN (Print) | 0738-100X |
Bibliographical note
Publisher Copyright:© 1998 ACM.
ASJC Scopus subject areas
- Computer Science Applications
- Control and Systems Engineering
- Electrical and Electronic Engineering
- Modeling and Simulation
- Hardware and Architecture