A Fast Back-to-Lock DPLL-Based 192&#x2013;210-GHz Chirp Generator With <inline-formula> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula>5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing

Lili Chen; Morteza Tavakoli Taba; Zainulabideen Khalifa; Andreia Cathelin; Ehsan Afshari

doi:10.1109/JSSC.2023.3317073

A Fast Back-to-Lock DPLL-Based 192–210-GHz Chirp Generator With <inline-formula> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula>5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing

Lili Chen, Morteza Tavakoli Taba, Zainulabideen Khalifa, Andreia Cathelin, Ehsan Afshari

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

A fully integrated high-efficiency phase-locked sub-terahertz (THz) radiator is reported in this article, implemented in a 55-nm SiGe BiCMOS process. This radiator is capable of generating 192–210-GHz chirps, which can be used for the new generation automotive and imaging radar systems. It consists of a low-power millimeter-wave digital phase-locked loop (DPLL)-based chirp generator, a high-efficiency 6<inline-formula> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> multiplier chain, and an on-chip folded slot antenna. By incorporating a 32-entry lookup table into the millimeter-wave DPLL, a fast back-to-lock feature is realized at the end of each chirp signal. In addition, this chirp generator prototype achieves <inline-formula> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula>5.9/<inline-formula> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula>19.2-dBm sub-THz power/effective isotropic radiated power (EIRP), which is among the highest in all the phase-locked sources at this frequency range. Its 3.0% dc-to-THz efficiency is at least 5<inline-formula> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> higher than all previously published works.

Original language	English
Pages (from-to)	1-14
Number of pages	14
Journal	IEEE Journal of Solid-State Circuits
DOIs	https://doi.org/10.1109/JSSC.2023.3317073
State	Accepted/In press - 2023
Externally published	Yes

Bibliographical note

Publisher Copyright:
IEEE

Keywords

Bandwidth
BiCMOS
Chirp
Generators
Imaging
Phase locked loops
Radar
Radar imaging
THz imaging
digital phase-locked loop (DPLL)
digitally controlled oscillator (DCO)
doubler
frequency chirp
frequency multiplier
phase-locked loop (PLL)
power amplifier (PA)
sub-terahertz (THz)
tripler

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.2023.3317073

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Chen, L., Taba, M. T., Khalifa, Z., Cathelin, A., & Afshari, E. (Accepted/In press). A Fast Back-to-Lock DPLL-Based 192–210-GHz Chirp Generator With <inline-formula> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula>5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing. IEEE Journal of Solid-State Circuits, 1-14. https://doi.org/10.1109/JSSC.2023.3317073

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title = "A Fast Back-to-Lock DPLL-Based 192–210-GHz Chirp Generator With $+$ 5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing",

abstract = "A fully integrated high-efficiency phase-locked sub-terahertz (THz) radiator is reported in this article, implemented in a 55-nm SiGe BiCMOS process. This radiator is capable of generating 192–210-GHz chirps, which can be used for the new generation automotive and imaging radar systems. It consists of a low-power millimeter-wave digital phase-locked loop (DPLL)-based chirp generator, a high-efficiency 6 $\times$ multiplier chain, and an on-chip folded slot antenna. By incorporating a 32-entry lookup table into the millimeter-wave DPLL, a fast back-to-lock feature is realized at the end of each chirp signal. In addition, this chirp generator prototype achieves $+$ 5.9/ $+$ 19.2-dBm sub-THz power/effective isotropic radiated power (EIRP), which is among the highest in all the phase-locked sources at this frequency range. Its 3.0% dc-to-THz efficiency is at least 5 $\times$ higher than all previously published works.",

keywords = "Bandwidth, BiCMOS, Chirp, Generators, Imaging, Phase locked loops, Radar, Radar imaging, THz imaging, digital phase-locked loop (DPLL), digitally controlled oscillator (DCO), doubler, frequency chirp, frequency multiplier, phase-locked loop (PLL), power amplifier (PA), sub-terahertz (THz), tripler",

author = "Lili Chen and Taba, {Morteza Tavakoli} and Zainulabideen Khalifa and Andreia Cathelin and Ehsan Afshari",

note = "Publisher Copyright: IEEE",

year = "2023",

doi = "10.1109/JSSC.2023.3317073",

language = "English",

pages = "1--14",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

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}

A Fast Back-to-Lock DPLL-Based 192–210-GHz Chirp Generator With <inline-formula> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula>5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing. / Chen, Lili; Taba, Morteza Tavakoli; Khalifa, Zainulabideen et al.
In: IEEE Journal of Solid-State Circuits, 2023, p. 1-14.

Research output: Contribution to journal › Article › peer-review

TY - JOUR

T1 - A Fast Back-to-Lock DPLL-Based 192–210-GHz Chirp Generator With $+$ 5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing

AU - Chen, Lili

AU - Taba, Morteza Tavakoli

AU - Khalifa, Zainulabideen

AU - Cathelin, Andreia

AU - Afshari, Ehsan

N1 - Publisher Copyright: IEEE

PY - 2023

Y1 - 2023

N2 - A fully integrated high-efficiency phase-locked sub-terahertz (THz) radiator is reported in this article, implemented in a 55-nm SiGe BiCMOS process. This radiator is capable of generating 192–210-GHz chirps, which can be used for the new generation automotive and imaging radar systems. It consists of a low-power millimeter-wave digital phase-locked loop (DPLL)-based chirp generator, a high-efficiency 6 $\times$ multiplier chain, and an on-chip folded slot antenna. By incorporating a 32-entry lookup table into the millimeter-wave DPLL, a fast back-to-lock feature is realized at the end of each chirp signal. In addition, this chirp generator prototype achieves $+$ 5.9/ $+$ 19.2-dBm sub-THz power/effective isotropic radiated power (EIRP), which is among the highest in all the phase-locked sources at this frequency range. Its 3.0% dc-to-THz efficiency is at least 5 $\times$ higher than all previously published works.

AB - A fully integrated high-efficiency phase-locked sub-terahertz (THz) radiator is reported in this article, implemented in a 55-nm SiGe BiCMOS process. This radiator is capable of generating 192–210-GHz chirps, which can be used for the new generation automotive and imaging radar systems. It consists of a low-power millimeter-wave digital phase-locked loop (DPLL)-based chirp generator, a high-efficiency 6 $\times$ multiplier chain, and an on-chip folded slot antenna. By incorporating a 32-entry lookup table into the millimeter-wave DPLL, a fast back-to-lock feature is realized at the end of each chirp signal. In addition, this chirp generator prototype achieves $+$ 5.9/ $+$ 19.2-dBm sub-THz power/effective isotropic radiated power (EIRP), which is among the highest in all the phase-locked sources at this frequency range. Its 3.0% dc-to-THz efficiency is at least 5 $\times$ higher than all previously published works.

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KW - BiCMOS

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KW - Generators

KW - Imaging

KW - Phase locked loops

KW - Radar

KW - Radar imaging

KW - THz imaging

KW - digital phase-locked loop (DPLL)

KW - digitally controlled oscillator (DCO)

KW - doubler

KW - frequency chirp

KW - frequency multiplier

KW - phase-locked loop (PLL)

KW - power amplifier (PA)

KW - sub-terahertz (THz)

KW - tripler

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DO - 10.1109/JSSC.2023.3317073

M3 - Article

AN - SCOPUS:85172996293

SN - 0018-9200

SP - 1

EP - 14

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

ER -