## Abstract

A fully integrated high-efficiency phase-locked sub-terahertz (THz) radiator is reported in this article, implemented in a 55-nm SiGe BiCMOS process. This radiator is capable of generating 192–210-GHz chirps, which can be used for the new generation automotive and imaging radar systems. It consists of a low-power millimeter-wave digital phase-locked loop (DPLL)-based chirp generator, a high-efficiency 6<inline-formula> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> multiplier chain, and an on-chip folded slot antenna. By incorporating a 32-entry lookup table into the millimeter-wave DPLL, a fast back-to-lock feature is realized at the end of each chirp signal. In addition, this chirp generator prototype achieves <inline-formula> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula>5.9/<inline-formula> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula>19.2-dBm sub-THz power/effective isotropic radiated power (EIRP), which is among the highest in all the phase-locked sources at this frequency range. Its 3.0% dc-to-THz efficiency is at least 5<inline-formula> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> higher than all previously published works.

Original language | English |
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Pages (from-to) | 1-14 |

Number of pages | 14 |

Journal | IEEE Journal of Solid-State Circuits |

DOIs | |

State | Accepted/In press - 2023 |

Externally published | Yes |

### Bibliographical note

Publisher Copyright:IEEE

## Keywords

- Bandwidth
- BiCMOS
- Chirp
- Generators
- Imaging
- Phase locked loops
- Radar
- Radar imaging
- THz imaging
- digital phase-locked loop (DPLL)
- digitally controlled oscillator (DCO)
- doubler
- frequency chirp
- frequency multiplier
- phase-locked loop (PLL)
- power amplifier (PA)
- sub-terahertz (THz)
- tripler

## ASJC Scopus subject areas

- Electrical and Electronic Engineering