A Fast Back-to-Lock DPLL-Based 192-210-GHz Chirp Generator With +5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing

Lili Chen; Morteza Tavakoli Taba; Zainulabideen Khalifa; Andreia Cathelin; Ehsan Afshari

doi:10.1109/JSSC.2023.3317073

A Fast Back-to-Lock DPLL-Based 192-210-GHz Chirp Generator With +5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing

Lili Chen^*
, Morteza Tavakoli Taba
, Zainulabideen Khalifa
, Andreia Cathelin
, Ehsan Afshari

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

A fully integrated high-efficiency phase-locked sub-terahertz (THz) radiator is reported in this article, implemented in a 55-nm SiGe BiCMOS process. This radiator is capable of generating 192-210-GHz chirps, which can be used for the new generation automotive and imaging radar systems. It consists of a low-power millimeter-wave digital phase-locked loop (DPLL)-based chirp generator, a high-efficiency 6times multiplier chain, and an on-chip folded slot antenna. By incorporating a 32-entry lookup table into the millimeter-wave DPLL, a fast back-to-lock feature is realized at the end of each chirp signal. In addition, this chirp generator prototype achieves +5.9/+19.2-dBm sub-THz power/effective isotropic radiated power (EIRP), which is among the highest in all the phase-locked sources at this frequency range. Its 3.0% dc-to-THz efficiency is at least 5times higher than all previously published works.

Original language	English
Pages (from-to)	1461-1474
Number of pages	14
Journal	IEEE Journal of Solid-State Circuits
Volume	59
Issue number	5
DOIs	https://doi.org/10.1109/JSSC.2023.3317073
State	Published - 1 May 2024

Bibliographical note

Publisher Copyright:
© 1966-2012 IEEE.

Keywords

BiCMOS
THz imaging
digital phase-locked loop (DPLL)
digitally controlled oscillator (DCO)
doubler
frequency chirp
frequency multiplier
phase-locked loop (PLL)
power amplifier (PA)
sub-terahertz (THz)
tripler

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/JSSC.2023.3317073

Cite this

@article{f808e35d351c4579a2a9eb0b24b4919c,

title = "A Fast Back-to-Lock DPLL-Based 192-210-GHz Chirp Generator With +5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing",

abstract = "A fully integrated high-efficiency phase-locked sub-terahertz (THz) radiator is reported in this article, implemented in a 55-nm SiGe BiCMOS process. This radiator is capable of generating 192-210-GHz chirps, which can be used for the new generation automotive and imaging radar systems. It consists of a low-power millimeter-wave digital phase-locked loop (DPLL)-based chirp generator, a high-efficiency 6times multiplier chain, and an on-chip folded slot antenna. By incorporating a 32-entry lookup table into the millimeter-wave DPLL, a fast back-to-lock feature is realized at the end of each chirp signal. In addition, this chirp generator prototype achieves +5.9/+19.2-dBm sub-THz power/effective isotropic radiated power (EIRP), which is among the highest in all the phase-locked sources at this frequency range. Its 3.0\% dc-to-THz efficiency is at least 5times higher than all previously published works.",

keywords = "BiCMOS, THz imaging, digital phase-locked loop (DPLL), digitally controlled oscillator (DCO), doubler, frequency chirp, frequency multiplier, phase-locked loop (PLL), power amplifier (PA), sub-terahertz (THz), tripler",

author = "Lili Chen and Taba, \{Morteza Tavakoli\} and Zainulabideen Khalifa and Andreia Cathelin and Ehsan Afshari",

note = "Publisher Copyright: {\textcopyright} 1966-2012 IEEE.",

year = "2024",

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language = "English",

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T1 - A Fast Back-to-Lock DPLL-Based 192-210-GHz Chirp Generator With +5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing

AU - Chen, Lili

AU - Taba, Morteza Tavakoli

AU - Khalifa, Zainulabideen

AU - Cathelin, Andreia

AU - Afshari, Ehsan

PY - 2024/5/1

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N2 - A fully integrated high-efficiency phase-locked sub-terahertz (THz) radiator is reported in this article, implemented in a 55-nm SiGe BiCMOS process. This radiator is capable of generating 192-210-GHz chirps, which can be used for the new generation automotive and imaging radar systems. It consists of a low-power millimeter-wave digital phase-locked loop (DPLL)-based chirp generator, a high-efficiency 6times multiplier chain, and an on-chip folded slot antenna. By incorporating a 32-entry lookup table into the millimeter-wave DPLL, a fast back-to-lock feature is realized at the end of each chirp signal. In addition, this chirp generator prototype achieves +5.9/+19.2-dBm sub-THz power/effective isotropic radiated power (EIRP), which is among the highest in all the phase-locked sources at this frequency range. Its 3.0% dc-to-THz efficiency is at least 5times higher than all previously published works.

AB - A fully integrated high-efficiency phase-locked sub-terahertz (THz) radiator is reported in this article, implemented in a 55-nm SiGe BiCMOS process. This radiator is capable of generating 192-210-GHz chirps, which can be used for the new generation automotive and imaging radar systems. It consists of a low-power millimeter-wave digital phase-locked loop (DPLL)-based chirp generator, a high-efficiency 6times multiplier chain, and an on-chip folded slot antenna. By incorporating a 32-entry lookup table into the millimeter-wave DPLL, a fast back-to-lock feature is realized at the end of each chirp signal. In addition, this chirp generator prototype achieves +5.9/+19.2-dBm sub-THz power/effective isotropic radiated power (EIRP), which is among the highest in all the phase-locked sources at this frequency range. Its 3.0% dc-to-THz efficiency is at least 5times higher than all previously published works.

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KW - frequency multiplier

KW - phase-locked loop (PLL)

KW - power amplifier (PA)

KW - sub-terahertz (THz)

KW - tripler

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A Fast Back-to-Lock DPLL-Based 192-210-GHz Chirp Generator With +5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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