A CMOS two-stage amplifier design methodology for CAD tools

Fathi A. Farag; Ahmed R. Mohamed; Ahmed Wahba

doi:10.1109/ICEEM52022.2021.9480624

A CMOS two-stage amplifier design methodology for CAD tools

Fathi A. Farag, Ahmed R. Mohamed, Ahmed Wahba

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents an automated design methodology for a CMOS two-stage operational amplifier as a basic analog building block. The proposed methodology relies on a set of complex-less mathematical equations based on a current-based MOSFET model, which describes all operating regions of the MOSFET. As a result, this design methodology offers an efficient, reliable, and fast method for transistor's sizing in high-performance analog integrated circuits without the need for the deep knowledge of an experienced analog-circuit designer. Moreover, a key feature of the proposed methodology is a trade-off between normalized total Current Excess Factor (CEF) and Area Excess Factor (AEF) of the circuit topology to achieve high power and area efficiency.

Original language	English
Title of host publication	ICEEM 2021 - 2nd IEEE International Conference on Electronic Engineering
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665418423
DOIs	https://doi.org/10.1109/ICEEM52022.2021.9480624
State	Published - 3 Jul 2021
Externally published	Yes
Event	2nd IEEE International Conference on Electronic Engineering, ICEEM 2021 - Menouf, Egypt Duration: 3 Jul 2021 → 4 Jul 2021

Publication series

Name	ICEEM 2021 - 2nd IEEE International Conference on Electronic Engineering

Conference

Conference	2nd IEEE International Conference on Electronic Engineering, ICEEM 2021
Country/Territory	Egypt
City	Menouf
Period	3/07/21 → 4/07/21

Bibliographical note

Publisher Copyright:
© 2021 IEEE.

Keywords

Area excess factor (AEF)
Automated analog circuit design
Current excess factor (CEF)
Two-stage amplifier

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ICEEM52022.2021.9480624

Cite this

Farag, F. A., Mohamed, A. R., & Wahba, A. (2021). A CMOS two-stage amplifier design methodology for CAD tools. In ICEEM 2021 - 2nd IEEE International Conference on Electronic Engineering Article 9480624 (ICEEM 2021 - 2nd IEEE International Conference on Electronic Engineering). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICEEM52022.2021.9480624

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title = "A CMOS two-stage amplifier design methodology for CAD tools",

abstract = "This paper presents an automated design methodology for a CMOS two-stage operational amplifier as a basic analog building block. The proposed methodology relies on a set of complex-less mathematical equations based on a current-based MOSFET model, which describes all operating regions of the MOSFET. As a result, this design methodology offers an efficient, reliable, and fast method for transistor's sizing in high-performance analog integrated circuits without the need for the deep knowledge of an experienced analog-circuit designer. Moreover, a key feature of the proposed methodology is a trade-off between normalized total Current Excess Factor (CEF) and Area Excess Factor (AEF) of the circuit topology to achieve high power and area efficiency.",

keywords = "Area excess factor (AEF), Automated analog circuit design, Current excess factor (CEF), Two-stage amplifier",

author = "Farag, \{Fathi A.\} and Mohamed, \{Ahmed R.\} and Ahmed Wahba",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 2nd IEEE International Conference on Electronic Engineering, ICEEM 2021 ; Conference date: 03-07-2021 Through 04-07-2021",

year = "2021",

month = jul,

day = "3",

doi = "10.1109/ICEEM52022.2021.9480624",

language = "English",

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Farag, FA, Mohamed, AR & Wahba, A 2021, A CMOS two-stage amplifier design methodology for CAD tools. in ICEEM 2021 - 2nd IEEE International Conference on Electronic Engineering., 9480624, ICEEM 2021 - 2nd IEEE International Conference on Electronic Engineering, Institute of Electrical and Electronics Engineers Inc., 2nd IEEE International Conference on Electronic Engineering, ICEEM 2021, Menouf, Egypt, 3/07/21. https://doi.org/10.1109/ICEEM52022.2021.9480624

A CMOS two-stage amplifier design methodology for CAD tools. / Farag, Fathi A.; Mohamed, Ahmed R.; Wahba, Ahmed.
ICEEM 2021 - 2nd IEEE International Conference on Electronic Engineering. Institute of Electrical and Electronics Engineers Inc., 2021. 9480624 (ICEEM 2021 - 2nd IEEE International Conference on Electronic Engineering).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Mohamed, Ahmed R.

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PY - 2021/7/3

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N2 - This paper presents an automated design methodology for a CMOS two-stage operational amplifier as a basic analog building block. The proposed methodology relies on a set of complex-less mathematical equations based on a current-based MOSFET model, which describes all operating regions of the MOSFET. As a result, this design methodology offers an efficient, reliable, and fast method for transistor's sizing in high-performance analog integrated circuits without the need for the deep knowledge of an experienced analog-circuit designer. Moreover, a key feature of the proposed methodology is a trade-off between normalized total Current Excess Factor (CEF) and Area Excess Factor (AEF) of the circuit topology to achieve high power and area efficiency.

AB - This paper presents an automated design methodology for a CMOS two-stage operational amplifier as a basic analog building block. The proposed methodology relies on a set of complex-less mathematical equations based on a current-based MOSFET model, which describes all operating regions of the MOSFET. As a result, this design methodology offers an efficient, reliable, and fast method for transistor's sizing in high-performance analog integrated circuits without the need for the deep knowledge of an experienced analog-circuit designer. Moreover, a key feature of the proposed methodology is a trade-off between normalized total Current Excess Factor (CEF) and Area Excess Factor (AEF) of the circuit topology to achieve high power and area efficiency.

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KW - Current excess factor (CEF)

KW - Two-stage amplifier

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M3 - Conference contribution

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T3 - ICEEM 2021 - 2nd IEEE International Conference on Electronic Engineering

BT - ICEEM 2021 - 2nd IEEE International Conference on Electronic Engineering

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2nd IEEE International Conference on Electronic Engineering, ICEEM 2021

Y2 - 3 July 2021 through 4 July 2021

ER -

A CMOS two-stage amplifier design methodology for CAD tools

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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Cite this