A Bit Addressable Register with Variable Write/Read Data widths

Aiman El-Maleh*, Saleh AlSaleh, Muhammad E.S. Elrabaa

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations
Original languageEnglish
Pages (from-to)9301-9303
Number of pages3
JournalArabian Journal for Science and Engineering
Issue number9
StatePublished - Sep 2021

Bibliographical note

Funding Information:
This work is supported by King Fahd University of Petroleum & Minerals under Project No. DF191015.


  • FIFO
  • FPGA
  • Variable data width buffer

ASJC Scopus subject areas

  • General

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