A Bit Addressable Register with Variable Write/Read Data widths

Aiman El-Maleh; Saleh AlSaleh; Muhammad E.S. Elrabaa

doi:10.1007/s13369-021-05550-6

A Bit Addressable Register with Variable Write/Read Data widths

Aiman El-Maleh^*, Saleh AlSaleh, Muhammad E.S. Elrabaa

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Original language	English
Pages (from-to)	9301-9303
Number of pages	3
Journal	Arabian Journal for Science and Engineering
Volume	46
Issue number	9
DOIs	https://doi.org/10.1007/s13369-021-05550-6
State	Published - Sep 2021

Bibliographical note

Funding Information:
This work is supported by King Fahd University of Petroleum & Minerals under Project No. DF191015.

Keywords

FIFO
FPGA
Variable data width buffer

ASJC Scopus subject areas

General

Access to Document

10.1007/s13369-021-05550-6

Cite this

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title = "A Bit Addressable Register with Variable Write/Read Data widths",

keywords = "FIFO, FPGA, Variable data width buffer",

author = "Aiman El-Maleh and Saleh AlSaleh and Elrabaa, {Muhammad E.S.}",

note = "Funding Information: This work is supported by King Fahd University of Petroleum & Minerals under Project No. DF191015.",

year = "2021",

month = sep,

doi = "10.1007/s13369-021-05550-6",

language = "English",

volume = "46",

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journal = "Arabian Journal for Science and Engineering",

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AU - El-Maleh, Aiman

AU - AlSaleh, Saleh

AU - Elrabaa, Muhammad E.S.

N1 - Funding Information: This work is supported by King Fahd University of Petroleum & Minerals under Project No. DF191015.

PY - 2021/9

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KW - FIFO

KW - FPGA

KW - Variable data width buffer

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U2 - 10.1007/s13369-021-05550-6

DO - 10.1007/s13369-021-05550-6

M3 - Article

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SN - 2193-567X

VL - 46

SP - 9301

EP - 9303

JO - Arabian Journal for Science and Engineering

JF - Arabian Journal for Science and Engineering

IS - 9

ER -