A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor with Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS

Austin Rovinski; Chun Zhao; Khalid Al-Hawaj; Paul Gao; Shaolin Xie; Christopher Torng; Scott Davidson; Aporva Amarnath; Luis Vega; Bandhav Veluri; Anuj Rao; Tutu Ajayi; Julian Puscar; Steve Dai; Ritchie Zhao; Dustin Richmond; Zhiru Zhang; Ian Galton; Christopher Batten; Michael B. Taylor; Ronald G. Dreslinski

doi:10.23919/VLSIC.2019.8778031

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor with Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS

Austin Rovinski
, Chun Zhao
, Khalid Al-Hawaj
, Paul Gao
, Shaolin Xie
, Christopher Torng
, Scott Davidson
, Aporva Amarnath
, Luis Vega
, Bandhav Veluri
, Anuj Rao
, Tutu Ajayi
, Julian Puscar
, Steve Dai
, Ritchie Zhao
, Dustin Richmond
, Zhiru Zhang
, Ian Galton
, Christopher Batten
, Michael B. Taylor

Ronald G. Dreslinski

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

18 Scopus citations

Abstract

This paper presents a 16nm 496-core RISC-V network-on-chip (NoC). The mesh achieves 1.4GHz at 0.98V, yielding a peak of 695 Giga RISC-V instructions/s (GRVIS) and a record 812,350 CoreMark benchmark score. The main feature is the NoC architecture, which uses only 1881μm² per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.

Original language	English
Title of host publication	2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C30-C31
ISBN (Electronic)	9784863487185
DOIs	https://doi.org/10.23919/VLSIC.2019.8778031
State	Published - Jun 2019
Externally published	Yes
Event	33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan Duration: 9 Jun 2019 → 14 Jun 2019

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2019-June

Conference

Conference	33rd Symposium on VLSI Circuits, VLSI Circuits 2019
Country/Territory	Japan
City	Kyoto
Period	9/06/19 → 14/06/19

Bibliographical note

Publisher Copyright:
© 2019 JSAP.

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.23919/VLSIC.2019.8778031

Cite this

Rovinski, A., Zhao, C., Al-Hawaj, K., Gao, P., Xie, S., Torng, C., Davidson, S., Amarnath, A., Vega, L., Veluri, B., Rao, A., Ajayi, T., Puscar, J., Dai, S., Zhao, R., Richmond, D., Zhang, Z., Galton, I., Batten, C., ... Dreslinski, R. G. (2019). A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor with Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers (pp. C30-C31). Article 8778031 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIC.2019.8778031

Rovinski, Austin ; Zhao, Chun ; Al-Hawaj, Khalid et al. / A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor with Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. pp. C30-C31 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

@inproceedings{61e4e8b8355c4a52a335160a6f231215,

title = "A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor with Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS",

abstract = "This paper presents a 16nm 496-core RISC-V network-on-chip (NoC). The mesh achieves 1.4GHz at 0.98V, yielding a peak of 695 Giga RISC-V instructions/s (GRVIS) and a record 812,350 CoreMark benchmark score. The main feature is the NoC architecture, which uses only 1881μm2 per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.",

author = "Austin Rovinski and Chun Zhao and Khalid Al-Hawaj and Paul Gao and Shaolin Xie and Christopher Torng and Scott Davidson and Aporva Amarnath and Luis Vega and Bandhav Veluri and Anuj Rao and Tutu Ajayi and Julian Puscar and Steve Dai and Ritchie Zhao and Dustin Richmond and Zhiru Zhang and Ian Galton and Christopher Batten and Taylor, \{Michael B.\} and Dreslinski, \{Ronald G.\}",

note = "Publisher Copyright: {\textcopyright} 2019 JSAP.; 33rd Symposium on VLSI Circuits, VLSI Circuits 2019 ; Conference date: 09-06-2019 Through 14-06-2019",

year = "2019",

month = jun,

doi = "10.23919/VLSIC.2019.8778031",

language = "English",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "C30--C31",

booktitle = "2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers",

address = "United States",

}

Rovinski, A, Zhao, C, Al-Hawaj, K, Gao, P, Xie, S, Torng, C, Davidson, S, Amarnath, A, Vega, L, Veluri, B, Rao, A, Ajayi, T, Puscar, J, Dai, S, Zhao, R, Richmond, D, Zhang, Z, Galton, I, Batten, C, Taylor, MB & Dreslinski, RG 2019, A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor with Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. in 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers., 8778031, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2019-June, Institute of Electrical and Electronics Engineers Inc., pp. C30-C31, 33rd Symposium on VLSI Circuits, VLSI Circuits 2019, Kyoto, Japan, 9/06/19. https://doi.org/10.23919/VLSIC.2019.8778031

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor with Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. / Rovinski, Austin; Zhao, Chun; Al-Hawaj, Khalid et al.
2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. p. C30-C31 8778031 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2019-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Rovinski, Austin

AU - Zhao, Chun

AU - Al-Hawaj, Khalid

AU - Gao, Paul

AU - Xie, Shaolin

AU - Torng, Christopher

AU - Davidson, Scott

AU - Amarnath, Aporva

AU - Vega, Luis

AU - Veluri, Bandhav

AU - Rao, Anuj

AU - Ajayi, Tutu

AU - Puscar, Julian

AU - Dai, Steve

AU - Zhao, Ritchie

AU - Richmond, Dustin

AU - Zhang, Zhiru

AU - Galton, Ian

AU - Batten, Christopher

AU - Taylor, Michael B.

AU - Dreslinski, Ronald G.

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N2 - This paper presents a 16nm 496-core RISC-V network-on-chip (NoC). The mesh achieves 1.4GHz at 0.98V, yielding a peak of 695 Giga RISC-V instructions/s (GRVIS) and a record 812,350 CoreMark benchmark score. The main feature is the NoC architecture, which uses only 1881μm2 per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.

AB - This paper presents a 16nm 496-core RISC-V network-on-chip (NoC). The mesh achieves 1.4GHz at 0.98V, yielding a peak of 695 Giga RISC-V instructions/s (GRVIS) and a record 812,350 CoreMark benchmark score. The main feature is the NoC architecture, which uses only 1881μm2 per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.

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M3 - Conference contribution

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SP - C30-C31

BT - 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers

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Y2 - 9 June 2019 through 14 June 2019

ER -

Rovinski A, Zhao C, Al-Hawaj K, Gao P, Xie S, Torng C et al. A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor with Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2019. p. C30-C31. 8778031. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.23919/VLSIC.2019.8778031

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor with Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS

Abstract

Publication series

Conference

Bibliographical note

ASJC Scopus subject areas

Access to Document

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Cite this