Design of Soft Error Tolerant Arithmetic Circuits

Arithmetic circuits, especially adders and multipliers, are the heart of any computing system that consists of several processing units ranging from small digital systems to supercomputers. As a result of the shrinking size of electronic devices, the rate of occurrence of soft errors has increased. Thus, designing soft error tolerant circuits is of great importance to cope with the increased vulnerability of digital systems to soft errors and to improve system reliability. Reliability of arithmetic circuits is usually enhanced by employing redundancy techniques. In this work, we propose an effective soft error tolerance design technique for arithmetic circuits that has minimum impact on performance, area and power. The proposed design is based on using fault tolerant C-element connecting a given output to one input of the C-element and connecting a delayed version of that output to the second input. Due to variable delay in the output bits of arithmetic circuits having the critical path at the most significant bit, larger delay will be added to the least significant bits than the most significant bits to guarantee fault tolerance against the largest pulse width for a given technology without impacting performance. In order not to impact the performance of the designed arithmetic circuit, it is not possible to add large delays at the most significant bits. To enhance fault tolerance for those bits, selective transistor redundancy will be applied. This is based on selectively duplicating and sizing a subset of the transistors to protect soft errors hitting critical transistors. We will apply our proposed approach to different adder and multiplier designs to evaluate their soft error tolerance and compare results with previously proposed designs in terms of soft error tolerance, design overhead including area, performance and power. The evaluation experiments will be based on simulations at the transistor level using SPICE to take care of all masking types including logical, electrical and latching-window masking.